The proper operation of CMOS logic, such as buffer amplifiers, requires that the inputs settle to levels near the power supply rails (such as VDD and ground) and that transition between these levels occurs crisply. The realities of system design, however, frequently prevent this from occurring, because the signal levels are not always crisply rail-to-rail, because of high speed analog effects, noise, or other causes.
In the past, CMOS input level-shifters addressed this problem by cascading multiple stages to achieve high net voltage gain around the switch points. This reduced the probability that an internal logic device would be exposed to indeterminate logic states. This approach, however, presents a design trade off. With fewer stages of gain, indeterminate levels result in increased power dissipation and risk of operation faults, while more gain stages have a greater net delay in the signal propagation.
It is desirable to provide an improved CMOS logic level-shifter which produces precise switching, even for slowly changing input signals, and which does not require multiple gain stages to achieve the crisp switching transitions.